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A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors.
Pavlos Maniotis
D. Fitsios
George T. Kanellos
Nikos Pleros
Published in:
OFC (2014)
Keyphrases
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multithreading
management system
associative memory
memory access
high speed
parallel implementation
response time
shared memory
high density
memory hierarchy
memory subsystem