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A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors.

Pavlos ManiotisD. FitsiosGeorge T. KanellosNikos Pleros
Published in: OFC (2014)
Keyphrases
  • multithreading
  • management system
  • associative memory
  • memory access
  • high speed
  • parallel implementation
  • response time
  • shared memory
  • high density
  • memory hierarchy
  • memory subsystem