StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures.
Arshyn ZhanbolatovKizheppatt VipinAresh DadlaniDmitriy FedorovPublished in: ARC (2020)
Keyphrases
- stochastic models
- network on chip
- interconnection networks
- routing algorithm
- fault tolerant
- stochastic model
- stochastic processes
- parallel algorithm
- multistage
- message passing
- parallel computers
- multi processor
- network simulator
- hardware implementation
- marginal distributions
- wireless sensor networks
- data transfer
- reinforcement learning
- ad hoc networks
- belief propagation
- random variables
- dynamic programming