Reducing test time with FPGA accelerators using OpenCL.
Timothy M. PlattChen LiuPublished in: NATW (2018)
Keyphrases
- field programmable gate array
- single chip
- hardware implementation
- low cost
- high speed
- parallel algorithm
- data sets
- real time
- embedded systems
- parallel computing
- low power consumption
- graphics processing units
- computing systems
- genetic algorithm
- statistical tests
- data acquisition
- information systems
- hardware design
- parallel architectures
- neural network