Deep Neural Network Training Accelerator Designs in ASIC and FPGA.
Shreyas K. VenkataramanaiahShihui YinYu CaoJae-Sun SeoPublished in: ISOCC (2020)
Keyphrases
- neural network training
- field programmable gate array
- application specific integrated circuits
- hardware implementation
- hardware architecture
- neural network
- xilinx virtex
- embedded systems
- training algorithm
- parallel computing
- image processing algorithms
- general purpose processors
- optimization method
- computing systems
- single chip
- signal processing
- back propagation
- decision making
- feature space
- efficient implementation
- feature extraction
- optimization algorithm
- fuzzy logic