Login / Signup

Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS.

Atsuki KobayashiKiichi Niitsu
Published in: IEEE Open J. Circuits Syst. (2020)
Keyphrases
  • low voltage
  • leakage current
  • cmos technology
  • learning microsoft office
  • design considerations
  • power line
  • peer to peer
  • random access memory
  • microsoft office
  • power management
  • low power
  • dynamic range
  • real time