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A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver.
Sander L. J. Gierkink
Dandan Li
Robert C. Frye
Vito Boccuzzi
Published in:
CICC (2004)
Keyphrases
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high speed
frequency response
phase locked loop
learning objects
low cost
frequency band
ultra low power
analog vlsi
dual band
real time
edge detection
power consumption
low power
single chip
filter design
low power consumption