A 32-core RISC microprocessor with network accelerators, power management and testability features.
Brian MillerDerek BrasiliTim KiszelyRob KuhnRahul MehrotraManan SalviMandar KulkarniAnand VaradharajanShi-Huang YinWilliam LinAdam HughesBill StysiackVasu KandadiIlan PragaspathiDan HartmanDavid CarlsonVishnu YalalaThucydides XanthopoulosScott E. MeningerEthan CrainMark SpaethAkin AinaSuresh BalasubramanianJoe VulihPragati TiwaryDavid LinRichard KesslerBruce FishbeinAnil JainPublished in: ISSCC (2012)