Node sensitivity analysis for soft errors in CMOS logic.
Balkaran S. GillChristos A. PapachristouFrancis G. WolffNorbert SeifertPublished in: ITC (2005)
Keyphrases
- sensitivity analysis
- delay insensitive
- managerial insights
- influence diagrams
- high speed
- variational inequalities
- low cost
- multi valued
- logic programming
- power consumption
- asynchronous circuits
- random access memory
- classical logic
- chip design
- circuit design
- directed graph
- graph structure
- tree structure
- digital circuits