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An output node split CMOS logic for high-performance and large capacitive-load driving scenarios.
Maliheh Rafiee
M. B. Ghaznavi-Ghoushchi
Published in:
Microelectron. J. (2018)
Keyphrases
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delay insensitive
low voltage
random access memory
embedded dram
power consumption
low cost
load balancing
chip design
low power consumption
real world
low power
image sensor
hidden nodes
high speed
multi valued
digital circuits
asynchronous circuits
input data