Low-power high-level synthesis using latches.
Woo-Seung YangIn-Cheol ParkChong-Min KyungPublished in: ASP-DAC (2001)
Keyphrases
- low power
- high level synthesis
- low cost
- power consumption
- high speed
- parallel architecture
- single chip
- wireless transmission
- high power
- design space exploration
- vlsi circuits
- digital signal processing
- cmos technology
- vlsi architecture
- logic circuits
- low power consumption
- signal processor
- power dissipation
- user interface
- mixed signal
- image segmentation
- efficient implementation
- graphical models