A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
Young-Ju KimHye-Jung KwonSu-Yeon DooMin-Su AhnYong-Hun KimYong Jae LeeDong-Seok KangSung-Geun DoChang-Yong LeeGun-hee ChoJae-Koo ParkJae-Sung KimKyung-Bae ParkSeung-Hoon OhSang-Yong LeeJi-Hak YuKi-Hun YuChul-Hee JeonSang-Sun KimHyun-Soo ParkJeong-Woo LeeSeung-Hyun ChoKeon-Woo ParkYong-Jun KimYoung-Hun SeoChang-Ho ShinChanYong LeeSam-Young BangYoun-Sik ParkSeouk-Kyu ChoiByung-Cheol KimGong-Heum HanSeung-Jun BaeHyuk-Jun KwonJung-Hwan ChoiYoung-Soo SohnKwang-Il ParkSeong-Jin JangGyo-Young JinPublished in: IEEE J. Solid State Circuits (2019)