Timing constraint specification and synthesis in behavioral VHDL.

Petru Eles Krzysztof Kuchcinski Zebo Peng Alexa Doboli

Published in: EURO-DAC (1995)

Keyphrases

asynchronous circuits
constraint language
program synthesis
data mining
specification language
hardware design
constraint solving
neural network
image processing
website
case study
low cost
integrated circuit
formal specification
linear constraints
behavioral model