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Impact of Single Event Upset on Voltage and Current Behaviors of CNTFET SRAM and a Comparison with CMOS SRAM.

T. R. RajalakshmiR. Sudhakar
Published in: J. Circuits Syst. Comput. (2017)
Keyphrases
  • low voltage
  • random access memory
  • power consumption
  • leakage current
  • low power
  • design considerations
  • power management
  • cmos technology
  • high speed
  • data transmission
  • power supply
  • neural network
  • power system