Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs.
Miroslav N. VelevPublished in: ITC (2003)
Keyphrases
- formal verification
- high level
- functional verification
- instruction set
- model checking
- low level
- source code
- model checker
- bounded model checking
- automated verification
- symbolic model checking
- high speed
- programs written
- higher level
- computer architecture
- temporal logic
- program slicing
- artificial intelligence
- multi agent systems
- circuit design
- application specific
- embedded systems