Decoder architecture for generalised concatenated codes.

Jens Spinner Jürgen Freudenberger

Published in: IET Circuits Devices Syst. (2015)

Keyphrases

error control
error correction
decoding algorithm
fpga implementation
real time
neural network
ldpc codes
feature vectors
management system
software architecture
low complexity
network architecture
error correcting codes
joint source channel
image compression