Login / Signup
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.
Avinash Karanth Kodi
Ashwini Sarathy
Ahmed Louri
Janet Meiling Wang
Published in:
ASP-DAC (2009)
Keyphrases
</>
network on chip
low power
power dissipation
cmos technology
power consumption
single chip
high speed
routing algorithm
low cost
packet switched
network simulator
multi processor
digital signal processing
interconnection networks
image sensor
data transfer
parallel architectures
multipath
parallel processing