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Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering.

S. M. Rezaul HasanYufridin Wahab
Published in: VLSI Design (2002)
Keyphrases
  • logic circuits
  • power dissipation
  • low power
  • power consumption
  • power reduction
  • chip design
  • flip flops
  • clock gating
  • low cost
  • high speed
  • mixed signal
  • cmos technology
  • digital signal processing
  • power saving
  • dynamic logic