Minimum separation layout for cmos circuits realizing tree-shape monotone decreasing logic circuits.
Yoshifumi ManabeKenichi HagiharaNobuki TokuraPublished in: Systems and Computers in Japan (1986)
Keyphrases
- logic circuits
- low power
- power consumption
- power dissipation
- high speed
- tunnel diode
- low cost
- logic synthesis
- cmos technology
- spatial layout
- spanning tree
- functional decomposition
- gate array
- vlsi circuits
- tree structure
- delay insensitive
- digital signal processing
- analog vlsi
- image sensor
- boolean functions
- real time
- object oriented