Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features.

Amitava Majumdar Balakrishna Jayadev

Published in: ATS (2018)

Keyphrases

high speed
image features
power consumption
logic programming
domain specific
co occurrence
feature set
low level
modal logic
data sets
feature vectors
object recognition
training data
feature extraction
high level
decision trees
neural network