A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores.

Venkata Syam P. Rapaka Diana Marculescu

Published in: ISLPED (2003)

Keyphrases

design process
single chip
case study
high speed
power consumption
parallel processing
computer architecture
high level synthesis
steady state
design principles
multi core processors
asynchronous communication
queueing theory
dynamic random access memory