Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices.
Juejian WuTianyu LiaoTaixin LiYixin XuVijaykrishnan NarayananYongpan LiuHuazhong YangXueqing LiPublished in: ICCAD (2023)
Keyphrases
- context aware
- mobile applications
- main memory
- embedded systems
- computing power
- memory usage
- memory hierarchy
- memory access
- prefetching
- memory subsystem
- memory requirements
- limited memory
- dynamic random access memory
- neural network
- memory bandwidth
- resource consumption
- storage devices
- data transfer
- computational power