CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore.

Avishek Choudhury Biplab K. Sikdar

Published in: DFT (2019)

Keyphrases

fault tolerant
low voltage
fault tolerance
virtual reality
power line
design considerations
distributed systems
load balancing
learning objects
main memory
memory management
query processing
state machine
e learning
real time
high speed
shared memory
cmos technology