Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.
Peiyi ZhaoJason McNeelyPradeep GolcondaMagdy A. BayoumiRobert A. BarcenasWeidong KuangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2007)
Keyphrases
- low power
- power consumption
- power dissipation
- high speed
- cmos technology
- flip flops
- low cost
- low power consumption
- edge detection
- single chip
- high power
- vlsi architecture
- logic circuits
- digital signal processing
- power reduction
- vlsi circuits
- wireless transmission
- real time
- gate array
- mixed signal
- multiple input
- image sensor
- pattern recognition