Sub-picosecond-jitter clock generation for interleaved ADC with Delay-Locked-Loop in 28nm CMOS.
Jianping GongSulin LiJohn A. McNeillPublished in: ISCAS (2016)
Keyphrases
- power consumption
- end to end delay
- high speed
- cmos technology
- nm technology
- power dissipation
- low power
- integrated circuit
- silicon on insulator
- analog to digital converter
- neural network
- metal oxide semiconductor
- generation process
- ad hoc networks
- low cost
- real time
- power management
- network resources
- low voltage
- packet loss rate
- packet loss