An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder.
Nikhil KikkeriPeter-Michael SeidelPublished in: ASAP (2007)
Keyphrases
- floating point
- fpga implementation
- floating point arithmetic
- hardware implementation
- fixed point
- square root
- instruction set
- floating point unit
- sparse matrices
- field programmable gate array
- transfer function
- signal processing
- information systems
- machine learning
- image enhancement
- fast fourier transform
- data management
- scheduling problem
- image processing