A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement.
Fazal HameedJerónimo CastrillónPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2019)
Keyphrases
- main memory
- memory subsystem
- memory access
- memory hierarchy
- design considerations
- image processing
- database management systems
- dynamic random access memory
- data structure
- energy consumption
- higher level
- external memory
- multithreading
- query processing
- caching scheme
- real time
- image enhancement
- parallel algorithm
- index structure
- wireless sensor networks
- low voltage