Low power design using double edge triggered flip-flops.

Razak Hossain Leszek D. Wronski Alexander Albicki

Published in: IEEE Trans. Very Large Scale Integr. Syst. (1994)

Keyphrases

low power
power dissipation
power consumption
single chip
low power consumption
low cost
cmos technology
high speed
logic circuits
digital signal processing
vlsi architecture
gate array
power reduction
mixed signal
high power
design process
flip flops
nm technology