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Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.
Charbel J. Akl
Rafic A. Ayoubi
Magdy A. Bayoumi
Published in:
ISQED (2009)
Keyphrases
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high speed
power consumption
low cost
data streams
process model
real time
case study
complex systems
complex networks
development process
power law
buffer size
duty cycle