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Robust, self-timed power-on reset circuit for low-voltage applications.

Vivek NautiyalGaurav SinglaLalit GuptaJitendra DasaniSagar DwivediMartin Kinkade
Published in: VLSI-SoC (2017)
Keyphrases
  • low voltage
  • power management
  • cmos technology
  • power consumption
  • low power
  • power line
  • design considerations
  • high speed
  • power dissipation
  • real time
  • collaborative learning
  • single phase
  • reactive power
  • digital images