Login / Signup
A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter.
Ahmed M. A. Ali
Christopher Dillon
Robert Sneed
Andrew S. Morgan
Scott Bardsley
John Kornblum
Lu Wu
Published in:
IEEE J. Solid State Circuits (2006)
Keyphrases
</>
analog to digital converter
radio frequency
relevance feedback
random sampling
monte carlo
data flow
feature selection
neural network
frequency band
sampling methods
linear array