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A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter.

Ahmed M. A. AliChristopher DillonRobert SneedAndrew S. MorganScott BardsleyJohn KornblumLu Wu
Published in: IEEE J. Solid State Circuits (2006)
Keyphrases
  • analog to digital converter
  • radio frequency
  • relevance feedback
  • random sampling
  • monte carlo
  • data flow
  • feature selection
  • neural network
  • frequency band
  • sampling methods
  • linear array