On-chip interconnection network for accelerator-rich architectures.

Jason Cong Michael Gill Yuchen Hao Glenn Reinman Bo Yuan

Published in: DAC (2015)

Keyphrases

interconnection networks
fault tolerant
multistage
parallel algorithm
message passing
routing algorithm
low cost
parallel implementation
parallel computers
high speed
distributed systems
wireless sensor networks
anomaly detection
intrusion detection
network traffic