A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.
Chua-Chin WangChi-Chun HuangChing-Li LeeTsai-Wen ChengPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2008)
Keyphrases
- low power
- high speed
- logic circuits
- single chip
- low power consumption
- power consumption
- vlsi architecture
- low cost
- digital signal processing
- gate array
- shift register
- mixed signal
- nm technology
- cmos technology
- power dissipation
- wireless transmission
- power reduction
- real time
- ultra low power
- frame rate
- energy dissipation
- delay insensitive
- high power
- vlsi circuits
- design process
- analog to digital converter
- signal processing
- image sensor
- data flow
- parallel processing