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70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing.

Ghafour Amouzad MahdirajiMohamad Khazani AbdullahMakhfudzah MokhtarAmin Malek MohammadiAhmad Fauzi AbasSafuraa Mohd BasirRaja Syamsul Azmir Raja Abdullah
Published in: Photonic Netw. Commun. (2010)
Keyphrases
  • duty cycle
  • clock frequency
  • high speed
  • power consumption
  • real time
  • low power
  • parallel computing
  • frequency band
  • cmos technology
  • image processing
  • low cost
  • frame rate
  • parallel architecture
  • frequency response