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A 16b 120MS/s Pipelined ADC Using an Auxiliary-Capacitor-Based Calibration Technique Achieving 90.5dB SFDR in 0.18 μm CMOS.
Haitao Liu
Jie Sun
Honglin Xu
Lizhen Zhang
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2022)
Keyphrases
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power supply
analog to digital converter
single chip
camera calibration
power consumption
high speed
hand eye coordination
data flow
database
focal length
camera parameters
vlsi circuits
multi view
cmos image sensor
low cost
stereo camera
analog vlsi