A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching.
Junghee LeeHyung Gyu LeeSoonhoi HaJongman KimChrysostomos NicopoulosPublished in: Conf. Computing Frontiers (2012)
Keyphrases
- prefetching
- response time
- processor array
- access patterns
- web prefetching
- web documents
- user perceived latency
- hit rate
- caching scheme
- access latency
- web caching
- management system
- scheduling algorithm
- computing systems
- web page prediction
- information extraction
- hit ratio
- general purpose processors
- operating system
- web logs
- hidden markov models
- natural language