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Minimizing inductive noise in system-on-a-chip with multiple power gating structures.
Suhwan Kim
Stephen V. Kosonocky
Daniel R. Knebel
Kevin Stawiasz
David F. Heidel
Michael Immediato
Published in:
ESSCIRC (2003)
Keyphrases
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image structure
machine learning
random noise
noise level
high density
neural network
low cost
high speed
inductive learning
ibm power processor
real time
noise model
additive noise
gaussian noise
computational power
noise reduction
data sets