Static ultra-low-voltage high-speed CMOS logic and latches.

Published in: VLSI-SoC (2010)

Keyphrases

high speed
low voltage
low power
cmos technology
random access memory
delay insensitive
power line
design considerations
power dissipation
asynchronous circuits
mixed signal
digital signal processing
power management
focal plane
image sensor
multi valued
frame rate
image sequences