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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

Burak ÇatliAli NazemiTamer A. AliSiavash FallahiYang LiuJaehyup KimMohammed M. Abdul-LatifMahmoud Reza AhmadiHassan MaarefiAfshin MomtazNamik Kocaman
Published in: CICC (2013)
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