A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.
Burak ÇatliAli NazemiTamer A. AliSiavash FallahiYang LiuJaehyup KimMohammed M. Abdul-LatifMahmoud Reza AhmadiHassan MaarefiAfshin MomtazNamik KocamanPublished in: CICC (2013)