On the design of low-voltage, low-power CMOS analog multipliers for RF applications.
Carl James DebonoFranco MalobertiJoseph MicallefPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2002)
Keyphrases
- low power
- mixed signal
- cmos technology
- low voltage
- vlsi circuits
- power consumption
- vlsi architecture
- high speed
- low cost
- single chip
- multi channel
- cmos image sensor
- digital signal processing
- analog to digital converter
- power dissipation
- low power consumption
- image sensor
- ultra low power
- logic circuits
- power reduction
- parallel processing
- power management
- digital circuits
- energy efficiency
- nm technology
- design considerations
- circuit design
- design methodology
- delay insensitive
- efficient implementation
- gate array
- computer vision and image processing