FPGA Bitstream Modification with Interconnect in Mind.
Michail MoraitisElena DubrovaPublished in: HASP@MICRO (2020)
Keyphrases
- bitstream
- high speed
- video decoder
- coding scheme
- bit rate
- compression algorithm
- video quality
- scalable video coding
- error resilient
- scalable video
- rate allocation
- error resilience
- coded video
- quality degradation
- wavelet coefficients
- compressed domain
- video transmission
- field programmable gate array
- error concealment
- real time
- hardware implementation
- frame rate
- pixel domain
- bit plane
- rate distortion optimized
- subband
- multiresolution
- low cost
- signal processing
- low power
- inter layer
- rate distortion
- low power consumption
- inter frame
- bit planes
- compressed video