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On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses.
Yajie Chen
Steve Hall
Liam McDaid
Octavian Buiu
Peter M. Kelly
Published in:
IJCNN (2006)
Keyphrases
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low power
power consumption
single chip
low cost
low power consumption
logic circuits
high speed
vlsi architecture
power dissipation
spiking neurons
cmos technology
digital signal processing
vlsi circuits
ultra low power
gate array
design methodology
power reduction
feature vectors