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Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA.
Nuray At
Jean-Luc Beuchat
Eiji Okamoto
Ismail San
Teppei Yamazaki
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2014)
Keyphrases
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high speed
real time image processing
hardware implementation
low cost
signal processing
field programmable gate array
bayesian networks
search algorithm
hardware architecture
systolic array
data sets
image processing
website
pattern recognition
hardware architectures