Input-aware statistical timing analysis for VLSI delay test and average design.
Bao LiuPublished in: MWSCAS (2014)
Keyphrases
- experimental design
- building blocks
- shortest path
- vlsi design
- power dissipation
- path length
- case study
- genetic algorithm
- neural network
- user interface
- high speed
- signal processing
- information systems
- database
- design process
- statistical models
- computer aided
- statistical tests
- statistical significance
- optimal design
- machine learning
- real time