Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching.
Zhiyuan ShaoRuoshi LiDiqing HuXiaofei LiaoHai JinPublished in: FPGA (2019)
Keyphrases
- real time
- reconfigurable hardware
- parallel architecture
- directed graph
- undirected graph
- low cost
- real time image processing
- labeled graphs
- minimum weight
- attributed graphs
- hamiltonian cycle
- connected components
- vertex set
- high speed
- graph theory
- hardware implementation
- data processing
- random walk
- field programmable gate array
- data acquisition
- strongly connected
- structured data
- spanning tree
- average degree
- weighted graph
- graph structure
- bipartite graph
- graph matching
- parallel processing
- main memory
- general purpose processors
- central processor
- hardware design
- high density
- directed acyclic graph
- data access
- query processing