An FPGA Based Memory Efficient Shared Buffer Implementation.

Dwayne Burns Ciaran Toal Kieran McLaughlin Sakir Sezer Mike Hutton Kevin Cackovic

Published in: FPL (2007)

Keyphrases

memory efficient
hardware architecture
hardware implementation
external memory
hardware architectures
real time
low cost
efficient implementation
information systems
data sets
case study
parallel implementation
hardware design
multiple sequence alignment
iterative deepening