On clock-aware LTL parameter synthesis of timed automata.
Peter BezdekNikola BenesIvana CernáJiri BarnatPublished in: J. Log. Algebraic Methods Program. (2018)
Keyphrases
- timed automata
- model checking
- temporal logic
- reachability analysis
- bounded model checking
- formal verification
- linear temporal logic
- parameter values
- theorem prover
- linear time temporal logic
- power consumption
- first order logic
- duty cycle
- parameter space
- theorem proving
- high speed
- program synthesis
- transition systems
- deterministic automata
- real time
- input parameters
- parameter settings
- modal logic
- knowledge base
- data sets