A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic.

W. A. J. Waller S. M. Aziz

Published in: VLSI (1993)

Keyphrases

high voltage
high speed
parallel computing
multi valued
classical logic
logic programming
power system
parallel implementation
interior point methods
modal logic
shared memory
floating point
operating conditions
logical framework
set theory