A New Low-Power Soft-Error Tolerant SRAM Cell.

Nicholas Axelos Kiamal Z. Pekmestzi Nikolaos Moschopoulos

Published in: ISVLSI (2010)

Keyphrases

low power
error tolerant
power consumption
high speed
low cost
graph matching
power reduction
low power consumption
digital signal processing
cmos technology
logic circuits
subgraph isomorphism
gate array
pattern recognition
computer vision
mixed signal
data mining