Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core.
Jens E. BeckerCarsten BieserAlexander ThomasKlaus D. Müller-GlaserJürgen BeckerPublished in: MSE (2003)
Keyphrases
- co training
- hardware software
- design methodology
- hardware architecture
- field programmable gate array
- hw sw
- hardware implementation
- embedded systems
- low power consumption
- semi supervised learning
- instruction set
- unlabeled data
- application specific
- multi view
- semi supervised
- single view
- text classification
- xilinx virtex
- supervised learning
- hardware design
- named entities
- training examples
- hardware and software
- design process
- programming language
- object oriented
- image processing algorithms
- parallel computing
- labeled data
- programming environment
- efficient implementation
- low cost
- active learning
- general purpose
- fuzzy neural network
- machine learning
- single chip