Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing.

Bo Fu Paul Ampadu

Published in: ICECS (2006)

Keyphrases

power dissipation
critical path
power consumption
low power
high speed
cmos technology
chip design
job shop scheduling problem
circuit design
power reduction
floating gate
vlsi circuits
delay insensitive
digital signal processing
power management
analog vlsi
objective function
power losses
low cost
scheduling problem